1. Field of the Invention
The present invention relates generally to semiconductor image detection systems. Specifically, the present invention relates to semiconductor image sensing array architectures and related processing methods for achieving high definition image sensing.
2. Description of the Prior Art
Semiconductor type image detection systems are commonly used for sensing images for a wide variety of applications including video systems, surveillance devices, robotics and machine vision, guidance systems, navigation systems, and computer inputs. FIG. 1 shows a schematic block diagram at 10 of a conventional semiconductor image detection system including a prior art image sensing array 12 of pixel unit cells 14 wherein the array includes m column bit lines 16, and n row address lines 18. The system further includes a row decoder 20, a column multiplexer 22 including m column readout circuits 23 coupled to receive data signals from the m column bit lines 16, a column decoder 24 connected to each of the column readout circuits 23 via a corresponding column select line 17, a timing control circuit 26, and an output processing circuit 28.
Each of the cells 14 includes a row address switch (not shown) coupled to receive a row address signal from row decoder 20 via a corresponding row address line 18. Each of the readout circuits 23 includes a column select switch (not shown) which is coupled to receive a column select signal from column decoder 24 via a corresponding column select line 17. Timing control circuit 26 provides timing control signals to row decoder 20, column decoder 24, and column multiplexer 22 for controlling operations of the system related to capture, flow, and processing of image data.
Each of the cells 14 includes an optical sensing element capable of detecting illumination at the coordinate location of array 12 at which the cell is disposed. Optical sensing elements commonly used in semiconductor arrays include charge coupled devices (CCD""s), photodiodes, pinned photodiodes, photogates, phototransistors, and charge injection devices. Typically, each cell is adapted to alternate between a light sensing mode wherein the cell outputs an image signal proportional to light detected by the optical sensing element and a reset mode wherein the cell may output a reset reference signal. The image signals and the reset reference signals comprise data signals which are provided to the column readout circuits 23 via the column bit lines 16.
A problem with image sensing using array 12 is that the voltage levels of the image signals provided by each cell 14 are small and sensitive to noise coupling and fixed pattern noise (FPN) caused by sensing amplifiers in the column readout circuits 23. Attenuation and noise problems increase as the number of cells 14 in array 12 increases because a larger sensing array requires longer column bit lines 16 for intercoupling the cells to the column readout circuits 23.
A pixel unit cell 14 may be either active or passive. In conventional passive pixel image sensor (PPS) systems, each of the cells 14 is a passive pixel unit cell (PPS cell) which includes an optical sensing element and electronic switching components for selectively coupling image signals between the optical sensing element and a sensing amplifier of a corresponding column readout circuit. In conventional active pixel image sensing (APS) systems, each of the cells 14 is an active pixel unit cell (APS cell) which includes active electronic components in addition to an optical sensing element and electronic switching components. The active electronic components such as, for example, source follower transistors in APS cells provide amplification of image signals generated by the optical sensing elements.
If PPS cells are employed as the pixel unit cells 14 in the image sensing array 12, each of the column bit lines 16 forms a sensing node for those cells 14 coupled to the column bit line. As the length of each of the column bit lines 16 increases, the parasitic capacitance of the column bit lines increases causing a decrease in the sensitivity of the image detecting system to light incident on the cells coupled to the column bit lines. As a result of increased parasitic capacitance, the data signals are attenuated and distorted as they are transmitted from the cells to the readout circuits 23 via the column bit lines. In other words, increased parasitic capacitance of the sensing nodes causes decreased voltage gain of the sensing nodes.
PPS technology provides advantages in fabrication over APS technology because the lithography process for fabricating sensing arrays using PPS cells is simple and manufacturing yield tends to be higher. PPS cells require less integrated circuit area, or chip real estate, than APS cells because PPS cells do not require the active electronic components that APS cells require.
APS technology provides performance advantages including increased sensitivity and immunity from noise. The active components in APS cells provide amplification of the data signals generated by the optical sensing elements. This amplification provides maintenance of image signal integrity as image signals propagate through longer column bit lines 16 in larger sensing arrays from the cells to the column readout circuits.
An additional advantage of APS technology is that the sensing node of each APS cell is isolated from the corresponding column bit line. Smaller sensing nodes have lower parasitic capacitance and therefore higher voltage gain. Also, the sensing nodes of APS cells allow for less cross coupling from other signal lines and are less sensitive to column circuit fixed pattern noise (FPN) than sensing nodes of PPS cells. Furthermore, the smaller sensing nodes of APS cells allow for lower kTC noise which is proportional to the number of electrons stored in the image sensing element of the cell. The kTC noise is proportional to the square root of the product, kTC. So it is desirable to minimize the size of sensing nodes of an image sensing array in order to minimize noise and maximize sensitivity. As discussed, this is commonly achieved by minimizing the size of an image sensing array.
It is also desirable to minimize the physical size of an image sensing array for ease of manufacturing, manufacturing yield, and portability. However, a conflicting goal in design of image detectors is to maximize the number of cells in the image sensing array because the definition, or resolution, of a detected image is a function of the number of pixels used to form the image. The overall size of an image sensing array depends on the number of cells in the array and the size of each cell in the array. Therefore it is desirable to increase the number of cells per unit area of an array by reducing the size of each pixel unit cell in order to maximize pixel density.
Fabrication of an APS cell using standard metal oxide semiconductor (MOS) technology typically requires an area which is approximately 10 xcexcmxc3x9710 xcexcm in size. Therefore, fabrication of an image sensing array having 4xc3x97106 pixels using standard MOS technology typically requires an area of approximately 2 cmxc3x972 cm. Due to integrated circuit manufacturing yield problems, fabrication of a 2 cmxc3x972 cm chip is not very practical. Using complementary metal oxide semiconductor (CMOS) technology, it is possible to fabricate an APS cell having an area which is approximately 5 xcexcmxc3x975 xcexcm in size. Fabrication of an image sensing array having 4xc3x97106 pixels using 0.5 xcexcm CMOS technology requires an area of approximately 400xc3x97300 mils.
In summary, while APS cells provide increased sensitivity and immunity to noise, it is difficult to achieve high pixel density image sensing arrays using APS technology because APS cells require a large integrated circuit area. PPS technology allows for fabrication of image sensing arrays which have high pixel density but are sensitive to noise problems.
It is therefore an object of the present invention to provide a semiconductor image detection system including a high density image sensing array of pixel unit cells wherein integrity of image data is not substantially degraded by parasitic capacitance and noise of sensing nodes.
Another object of the present invention is to provide a system of the type described wherein the sensing array is subdivided into area components in which groups of cells are communicatively coupled to the column bit lines through common connections.
Another object of the present invention is to provide a system of the type described wherein the cell data from cells within predetermined groups of cells are read out to column bit lines through shared amplifying circuits
Briefly, a presently preferred embodiment of the present invention includes an image sensing array of photo responsive semiconductor cells that is segmented into blocks of cells, with each column of cells within each block including a reader cell connected to each sensing cell in the column block and adapted to selectively communicate image data to an associated column bit line via an amplifier means formed within the reader cell.
An important advantage of this invention is that since photo cell signals are amplified before they are output to a column bit line, substantial improvement in signal to noise ratio can be obtained over conventional image sensing arrays using passive pixel sensing technology. Another advantage is that the sensing cells used in the present invention do not include amplifiers and therefore enable higher cell density and resulting higher image sensitivity and definition than conventional image sensing arrays using active pixel sensing technology.